The present invention relates to an emitter coupled logic (to be referred to as an ECL hereinafter) latch circuit and, more particularly, to a latch circuit having a set or reset function.
FIG. 3 shows the arrangement of a conventional ECL latch circuit having a reset function. Referring to FIG. 3, reference symbol EF1 denotes an input emitter follower section; L3, a logic section; EF3, an output emitter follower section; and EF4, an internal emitter follower section.
The input emitter follower section EF1 has a transistor Q1 and a resistor R3. The internal emitter follower section EF4 has transistors Q11 and Q12 and resistors R4, R7, R8, and R9. The logic section L3 has transistors Q2, Q3, Q4, Q5, Q6, Q7, and Q8, resistors R1 and R2, and a constant current source CS, in addition to the internal emitter follower section EF4.
The output emitter follower section EF3 also includes transistors Q9 and Q10 and resistors R5 and R6.
When a latch strobe signal input to a latch strobe signal input terminal TE is at high level, the transistor Q1 of the input emitter follower section EF1 is turned on. As a result, the transistor Q7 is turned on. One of the transistors Q3, Q4, and Q6 which has the highest base potential is also turned on to determine a logical value.
In this case, signals input to the bases of the transistors Q3 and Q4 are level-shifted by the resistors R7 and R8 so that the high level of a signal at a reset signal input terminal TRE becomes higher than the base potentials of both the transistors Q3 and Q4. With this setting, a reset function is ensured. As such a circuit, an ECL gate array latch circuit available from Motorola/UDS is disclosed in the MACROCELL ARRAYS MCA2500ECL design manual (p. 6).
Similar to the ECL latch circuit shown in FIG. 3, a conventional ECL latch circuit having a set function is designed such that the high level of a set signal becomes higher than the base potentials of both transistors Q3 and Q4 by using level shift resistors, as shown in FIG. 4.
In the conventional ECL latch circuit having the reset function shown in FIG. 3, if level shifts performed by the level shift resistors R7 and R8 are too large, the emitter potentials of the transistors Q3 and Q4 are decreased too much, resulting in saturation of the transistor Q7, or a current flowing in the internal emitter follower section EF4 decreases, resulting in a decrease in operation speed.
For this reason, the level shifts in the conventional latch circuit are set to be about 150 mV. Assume that the logic amplitude of the circuit is 600 mV, that the potential difference between the base and emitter of each of the transistors Q11 and Q12 is 800 mV, and that a supply voltage VE is -4.5 V. In this case, a potential difference between the resistors R9 and R4 becomes 3.55 V in a high-level state, and 2.95 V in a low-level state. Since a current flowing in the resistors R7 and R4 is equal to a current flowing in the resistors R8 and R9, the resistance of the level shift resistors R7 and R8 is about 1/20 to 1/24 that of the emitter follower resistors R9 and R4.
If, therefore, all resistors are formed of optimal layer resistors for the frequently used emitter follower resistors, the width of a level shifter resistor becomes several time larger than that of a emitter follower resistor even if the length of the level shift resistor is decreased as much as possible in terms of reliability and fabrication. Consequently, the level shift register has an extremely large element area, resulting in an increase in overall circuit area.
Especially in an ECL gate array, the above-described level shift resister must be arranged in each cell, regardless of whether the resistor is used or not, in order to allow a latch circuit with a set or reset function to be formed in any internal cell. Therefore, the overall chip area is inevitably increased regardless of whether a latch circuit with a set or reset function is used or not.
The difference between the high level of the reset signal and the high level of the base potential of each of the transistors Q3 and Q4 is about 150 mV, which is about half a normal logic noise margin of 300 mV (half a logic amplitude of 600 mV). For this reason, operation errors tend to occur.
Note that the problems in the above-described conventional latch circuit with the reset function are the same as those in a latch circuit with a set function.